1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly, relates to a source and drain structure in an MISFET.
2. Related Art
In recent years, along with the miniaturization and high integration of a metal-insulator-semiconductor field-effect-transistor (MISFET) having a structure obtained by combining three different “metal-insulating film-semiconductor” substances, a diffusion layer has become smaller in depth, and a sidewall spacer has become narrower in width. Herein, the metal is used in a broad sense, including not only a pure metal, but also a semiconductor material having a sufficiently large conductivity or an alloy of the semiconductor and the metal and the like.
The MISFET generally includes a channel region, a gate insulating film, a gate electrode, a source region, and a drain region, regardless of an n-channel conductivity type and a p-channel conductivity type. The diffusion layer refers to the source region and the drain region among these, and, in a region in the vicinity of a gate of the source region and drain region, a region of the diffusion layer called an extension region becomes shallower.
Miniaturization of the MISFET is realized by reducing the width of the gate electrode, decreasing the thickness of the gate insulating film, and reducing the thickness of the extension region. In addition, for the purpose of achieving high integration of the MISFET, it is required to reduce the width of the sidewall spacer in addition to these operations.
The following analyses are given by the present inventor. Japanese Unexamined Patent Publication Nos. 2003-309079, 2005-183550 and 2006-108142 disclose a method of implanting the ions, such as germanium and the like, having a large mass before the formation of the source and drain region, and breaking down (amorphizing) the lattice crystal of the surface of semiconductor substrate, in order to suppress the expansion of the impurity region in a transverse direction at the time of the formation of the source and drain region.
However, there is a problem, in this method, that crystal defects generated by the implantation are extremely large. With the drastic development of scaling in recent years, the prevailing trend is that the impurities are activated through high-temperature millisecond annealing by which little impurity diffusion is brought about. In such an activation method, the defects cannot be completely recovered by amorphization of the substrate surface using germanium and the like, thereby generating an extremely large junction leakage current.
In Japanese Unexamined Patent Publication Nos. 2003-309079, 2005-183550 and 2006-108142 mentioned above, it cannot be said to be sufficient that such defects are reduced as much as possible by the conditions of high-temperature millisecond annealing and the like.
In addition, Japanese Unexamined Patent Publication Nos. 2003-309079, 2005-183550, 2006-186349 and 2006-005373 disclose a method of amorphization with not only germanium but also the same conductivity-type ions having a large mass, using the same conductivity-type plural impurities having a different mass. However, such an element having a large mass also causes great damage to the substrate, and its use in large quantities generates numerous crystal defects in the substrate. Consequently, when only the high-temperature millisecond annealing is applied, the defects cannot be completely recovered, thereby bringing about an increase in the junction leakage.
A correlation between the implantation amount of indium which is a p-type conductive material and the thickness of an amorphous layer formed after the implantation is shown in FIG. 2 of T. Noda, S. Odanaka, H. Umimoto ‘Effects of end-of-range dislocation loops on transient enhanced diffusion of indium implanted in silicon’ Journal of Applied Physics Vol 88 No 9 p. 4980-4984 2000. According to the same drawing, the relationship of the thicknesses of the amorphous layer with respect to the implantation amount is different when the implantation amount of indium is up to 1E14 atoms/cm2 and when the amount is equal to or more than this value. This is considered to be because when the implantation of the amount equal to or more than 1E14 atoms/cm2 is performed, the amorphous layer is formed up to the depth to which indium is implanted into the substrate by the impurity implantation. When the amorphous layer is deeply formed in this way, the crystal defects cannot be recovered without performing sufficient heat treatment. Consequently, from the viewpoint that the amorphous layer is not deeply formed in the substrate, it is preferable that the implantation amount of the element to be implanted is equal to or less than 1E14 atoms/cm2.
In Japanese Unexamined Patent Publication Nos. 2003-31798 and 2005-33098, the deep portion in the source and drain region is formed with the implantation amount of indium which is a p-type impurity heavier than boron. In addition, the generation of the defects is suppressed by suppressing the implantation amount thereof to 2.5E13 atoms/cm2.
However, in the semiconductor device disclosed in Japanese Unexamined Patent Publication Nos. 2003-31798 and 2005-33098, there is a problem that an increase in the junction leakage is exhibited under the application of the high-temperature millisecond annealing.
The cause of the junction leakage increasing is that there is no controllability in a position of the heavier ions to be implanted, and ions intruding more deeply than the effective depth by the high-temperature millisecond annealing are generated. By using the channeling phenomenon, the impurities are implanted more deeply than the depth to be assumed from the impurity implantation energy used in order to deeply dispose the ions. Since the high-temperature millisecond annealing has a very short period of heating time, the rear surface of the wafer is not heated.
A correlation between temperature and depth from the surface of the wafer when the typical high-temperature millisecond annealing is applied is shown in FIG. 2 of Chen Shaoyin, J. Hebb, A. Jain, S. Shetty, Wang Yun, ‘Wafer Temperature Measurement and Control During Laser Spike Annealing’, 15th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2007. pp. 239-244, 2007. According to this, it is known that the temperature is drastically lowered even at a surface temperature of 1400° C. In the method disclosed in Japanese Unexamined Patent Publication No. 2003-31798, the generated crystal defects are certainly small because of a small implantation amount of the impurities. However, when the defects are formed in a deeper position than expected, the heat treatment temperature is lowered, and thus an increase in the junction leakage is brought about.
In addition, as a result of the fact that the width of the sidewall spacer is also reduced with scaling of the transistor, the influence of not only the extension region but also the source and drain region on the transistor characteristics becomes larger. This is because when ions are implanted in the source and drain region, ions changing in a traveling direction are generated by the collision with the crystal of the substrate, and thus there is a phenomenon of the ions intruding in a channel direction. For this reason, the source and the drain come close to each other, and thus a drop in the threshold voltage or an increase in the off current is brought about. Therefore, in the method disclosed in Japanese Unexamined Patent Publication Nos. 2003-31798 and 2005-33098 which use channeling, an increase in variation of the threshold voltage or the off current is brought about.